
module core (
input           clk,     // clk input
input           rst_n,     // CPU rst_n
output [31:0]   maddr,     // Read/Write address 
output          wenable,   // Write enable 
output [31:0]   wdata,     // Write data 
output          renable,   // Read enable 
input  [31:0]   rdata,     // Read data 
input           m_ok,      // Read & write addresses within range 
output [31:0]   pc,        // Instruction address 
input  [31:0]   instr,     // 4 bytes of instruction 
output          i_ok,      // Instruction address within range 
output [2:0]    stat      // CPU status
   );


/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire                    D_bubble;               // From U_pipeCntl of pipeCntl.v
wire                    D_stall;                // From U_pipeCntl of pipeCntl.v
wire                    E_bubble;               // From U_pipeCntl of pipeCntl.v
wire                    E_stall;                // From U_pipeCntl of pipeCntl.v
wire                    F_bubble;               // From U_pipeCntl of pipeCntl.v
wire                    F_stall;                // From U_pipeCntl of pipeCntl.v
wire                    M_bubble;               // From U_pipeCntl of pipeCntl.v
wire                    M_stall;                // From U_pipeCntl of pipeCntl.v
wire                    W_bubble;               // From U_pipeCntl of pipeCntl.v
wire                    W_stall;                // From U_pipeCntl of pipeCntl.v
wire [3:0]              d_dstE;                 // From U_decode of decode.v
wire [3:0]              d_dstM;                 // From U_decode of decode.v
wire [7:0]              d_opcode;                // From U_decode of decode.v
wire [1:0]              d_opcode_supp;                 // From U_decode of decode.v
wire [3:0]              d_srcA;                 // From U_decode of decode.v
wire [3:0]              d_srcB;                 // From U_decode of decode.v
wire [2:0]              d_stat;                 // From U_decode of decode.v
wire [31:0]             d_valA;                 // From U_decode of decode.v
wire [31:0]             d_valB;                 // From U_decode of decode.v
wire [31:0]             d_valImm;                 // From U_decode of decode.v
wire                    e_cnd;                  // From U_execute of execute.v
wire [3:0]              e_dstE;                 // From U_execute of execute.v
wire [3:0]              e_dstM;                 // From U_execute of execute.v
wire [7:0]             e_opcode;                // From U_execute of execute.v
wire [1:0]             e_opcode_supp;                 // From U_execute of execute.v
wire [2:0]              e_stat;                 // From U_execute of execute.v
wire [31:0]             e_valA;                 // From U_execute of execute.v
wire [31:0]             e_valE;                 // From U_execute of execute.v
wire [7:0]              f_opcode;                // From U_fetch of fetch.v
wire [1:0]              f_opcode_supp;                 // From U_fetch of fetch.v
wire [31:0]             f_pc;                   // From U_fetch of fetch.v
wire [3:0]              f_rA;                   // From U_fetch of fetch.v
wire [3:0]              f_rB;                   // From U_fetch of fetch.v
wire [2:0]              f_stat;                 // From U_fetch of fetch.v
wire [31:0]             f_valImm;                 // From U_fetch of fetch.v
wire                    m_cnd;                  // From U_memory of memory.v
wire [3:0]              m_dstE;                 // From U_memory of memory.v
wire [3:0]              m_dstM;                 // From U_memory of memory.v
wire [7:0]              m_opcode;                // From U_memory of memory.v
wire [2:0]              m_stat;                 // From U_memory of memory.v
wire [31:0]             m_valA;                 // From U_memory of memory.v
wire [31:0]             m_valE;                 // From U_memory of memory.v
wire [31:0]             m_valM;                 // From U_memory of memory.v
wire [3:0]              w_dstE;                 // From U_wrtbak of wrtbak.v
wire [3:0]              w_dstM;                 // From U_wrtbak of wrtbak.v
wire [7:0]              w_opcode;                // From U_wrtbak of wrtbak.v
wire [2:0]              w_stat;                 // From U_wrtbak of wrtbak.v
wire [31:0]             w_valE;                 // From U_wrtbak of wrtbak.v
wire [31:0]             w_valM;                 // From U_wrtbak of wrtbak.v
// End of automatics

// Pass throught signal
assign pc = f_pc;
assign stat = w_stat;

pipeCntl U_pipeCntl ( /*AUTOINST*/
                     // Outputs
                     .F_stall           (F_stall),
                     .F_bubble          (F_bubble),
                     .D_stall           (D_stall),
                     .D_bubble          (D_bubble),
                     .E_stall           (E_stall),
                     .E_bubble          (E_bubble),
                     .M_stall           (M_stall),
                     .M_bubble          (M_bubble),
                     .W_stall           (W_stall),
                     .W_bubble          (W_bubble),
                     // Inputs
                     .d_opcode           (d_opcode[7:0]),
                     .d_srcA            (d_srcA[3:0]),
                     .d_srcB            (d_srcB[3:0]),
                     .e_opcode           (e_opcode[7:0]),
                     .e_dstM            (e_dstM[3:0]),
                     .e_cnd             (e_cnd),
                     .m_opcode           (m_opcode[7:0]),
                     .m_stat            (m_stat[2:0]),
                     .w_opcode           (w_opcode[7:0]),
                     .w_stat            (w_stat[2:0]));
fetch   U_fetch     ( /*AUTOINST*/
                     // Outputs
                     .f_pc              (f_pc[31:0]),
                     .f_opcode           (f_opcode[7:0]),
                     .f_opcode_supp            (f_opcode_supp[1:0]),
                     .f_rA              (f_rA[3:0]),
                     .f_rB              (f_rB[3:0]),
                     .f_valImm            (f_valImm[15:0]),
                     .f_stat            (f_stat[2:0]),
                     // Inputs
                     .clk             (clk),
                     .rst_n             (rst_n),
                     .i_ok              (i_ok),
                     .instr             (instr[31:0]),
                     .w_opcode           (w_opcode[7:0]),
                     .m_opcode           (m_opcode[7:0]),
                     .m_valA            (m_valA[31:0]),
                     .w_valM            (w_valM[31:0]),
                     .m_cnd             (m_cnd),
                     .F_stall           (F_stall),
                     .F_bubble          (F_bubble),
		    
							.m_stat(m_stat)
		 );
decode  U_decode    ( /*AUTOINST*/
                     // Outputs
                     .d_opcode           (d_opcode[7:0]),
                     .d_stat            (d_stat[2:0]),
                     .d_valImm            (d_valImm[15:0]),
                     .d_valA            (d_valA[31:0]),
                     .d_valB            (d_valB[31:0]),
                     .d_dstE            (d_dstE[3:0]),
                     .d_dstM            (d_dstM[3:0]),
                     .d_srcA            (d_srcA[3:0]),
                     .d_srcB            (d_srcB[3:0]),
                     // Inputs
                     .clk             (clk),
                     .rst_n             (rst_n),
                     .f_opcode           (f_opcode[7:0]),
                     .f_stat            (f_stat[2:0]),
                     .f_rA              (f_rA[3:0]),
                     .f_rB              (f_rB[3:0]),
                     .f_valImm            (f_valImm[15:0]),                     
                     .m_cnd             (m_cnd),
                     .e_dstE            (e_dstE[3:0]),
                     .e_valE            (e_valE[31:0]),
                     .m_valE            (m_valE[31:0]),
                     .m_dstE            (m_dstE[3:0]),
                     .m_valM            (m_valM[31:0]),
                     .m_dstM            (m_dstM[3:0]),
                     .w_valE            (w_valE[31:0]),
                     .w_dstE            (w_dstE[3:0]),
                     .w_valM            (w_valM[31:0]),
                     .w_dstM            (w_dstM[3:0]),
                     .w_wordselE(w_wordselE[1:0]),
                     .w_wordselM(w_wordselM[1:0]),
                     .D_stall           (D_stall),
                     .D_bubble          (D_bubble));
execute U_execute   ( /*AUTOINST*/
                     // Outputs
                     .e_opcode           (e_opcode[7:0]),                     
                     .e_valE            (e_valE[31:0]),
                     .e_valA            (e_valA[31:0]),
                     .e_dstE            (e_dstE[3:0]),
                     .e_dstM            (e_dstM[3:0]),
                     .e_cnd             (e_cnd),
                     .e_stat            (e_stat[2:0]),
                     // Inputs
                     .clk             (clk),
                     .rst_n             (rst_n),
                     .d_opcode           (d_opcode[7:0]),
                     .d_stat            (d_stat[2:0]),
                     .d_dstE            (d_dstE[3:0]),
                     .d_dstM            (d_dstM[3:0]),
                     .d_valImm            (d_valImm[15:0]),
                     .d_valB            (d_valB[31:0]),
                     .d_valA            (d_valA[31:0]),
                     .m_stat            (m_stat[2:0]),
                     .w_stat            (w_stat[2:0]),
                     .E_stall           (E_stall),
                     .E_bubble          (E_bubble));
memaccess  U_memaccess    ( /*AUTOINST*/
                     // Outputs
                     .maddr             (maddr[31:0]),
                     .wenable           (wenable),
                     .wdata             (wdata[31:0]),
                     .renable           (renable),
                     .m_opcode           (m_opcode[7:0]),
                     .m_valM            (m_valM[31:0]),
                     .m_valE            (m_valE[31:0]),
                     .m_valA            (m_valA[31:0]),
                     .m_dstM            (m_dstM[3:0]),
                     .m_dstE            (m_dstE[3:0]),
                     .m_stat            (m_stat[2:0]),
                     .m_cnd             (m_cnd),
                     // Inputs
                     .clk             (clk),
                     .rst_n             (rst_n),
                     .e_opcode           (e_opcode[7:0]),
                     .e_valE            (e_valE[31:0]),
                     .e_valA            (e_valA[31:0]),
                     .e_dstE            (e_dstE[3:0]),
                     .e_dstM            (e_dstM[3:0]),
                     .e_stat            (e_stat[2:0]),
                     .e_cnd             (e_cnd),
                     .rdata             (rdata[31:0]),
                     .m_ok              (m_ok),
                     .M_stall           (M_stall),
                     .M_bubble          (M_bubble));
wrtbak  U_wrtbak    ( /*AUTOINST*/
                     // Outputs
                     .w_opcode           (w_opcode[7:0]),
                     .w_valM            (w_valM[31:0]),
                     .w_valE            (w_valE[31:0]),
                     .w_dstM            (w_dstM[3:0]),
                     .w_dstE            (w_dstE[3:0]),
                     .w_stat            (w_stat[2:0]),
                     // Inputs
                     .clk             (clk),
                     .rst_n             (rst_n),
                     .m_opcode           (m_opcode[7:0]),
                     .m_valM            (m_valM[31:0]),
                     .m_valE            (m_valE[31:0]),
                     .m_dstM            (m_dstM[3:0]),
                     .m_dstE            (m_dstE[3:0]),
                     .m_stat            (m_stat[2:0]),
                     .W_stall           (W_stall),
                     .W_bubble          (W_bubble));

endmodule

